A buffer minimization problem for the design of embedded systems

We consider a set of n tasks, each of them is composed by a set of sequential operations. A set of bu ers B is given : each bu er b 2 B is de ned between two tasks Ti ! Tj , has a weight wb and is managed as a FIFO structure. Some operations from Ti write data in the bu er b, other from Tj get data in b. The writings and readings on bu ers generate precedence constraints between the operations. The limitation of the size of the bu ers generates an other set of precedence constraints between them and circuits in this precedence graph may appear. In this case, there is no feasible schedule for the operations. The aim is to nd the size of each bu er (b); b 2 B such that P b2B wb (b) is minimum and there is no circuit in the precedence graph. We prove that this problem is polynomial for 2 tasks using a ow algorithm. We also prove that it is NP-hard in the strong sense for 3 tasks.